Customizable Embedded Processors

Customizable processors have been described as the next natural step in the evolution of the microprocessor business: a step in the life of a new technology where top performance alone is no longer sufficient to guarantee market success. Other factors become fundamental, such as time to market, convenience, energy efficiency, and ease of customization.

This book is the first to explore comprehensively one of the most fundamental trends which emerged in the last decade: to treat processors not as rigid, fixed entities, which designers include “as is” in their products; but rather, to build sound methodologies to tailor-fit processors to the specific needs of such products. This book addresses the goal of maintaining a very large family of processors, with a wide range of features, at a cost comparable to that of maintaining a single processor.

  • First book to present comprehensively the major ASIP design methodologies and tools without any particular bias.
  • Written by most of the pioneers and top international experts of this young domain.
  • Unique mix of management perspective, technical detail, research outlook, and practical implementation.

Table of Contents
Part I: Opportunities and Challenges
Chapter 1. From Prêt-à-Porter to Tailor-Made
Chapter 2. Opportunities for Application-Specific Processors: The Case of Wireless Communications
Chapter 3. Customizing Processors: Lofty Ambitions,

Part II: Aspects of Processor Customization
Chapter 4. Architecture Description Languages
Chapter 5. C Compiler Retargeting
Chapter 6. Automated Processor Configuration and Instruction Extension
Chapter 7. Automatic Instruction-Set Extensions
Chapter 8. Challenges to Automatic Customization
Chapter 9. Coprocessor Generation from Executable Code
Chapter 10. Datapath Synthesis
Chapter 11. Instruction Matching and Modeling
Chapter 12. Processor Verification
Chapter 13. Sub-RISC Processors

Part III: Case Studies
Chapter 14. Application Specific Instruction Set Processor for UMTS-FDD Cell Search
Chapter 15. Hardware/Software Tradeoffs for Advanced 3G Channel Decoding
Chapter 16. Application Code Profiling and ISA Synthesis on MIPS32
Chapter 17. Designing Soft Processors for FPGAs

Book Details

  • Hardcover: 528 pages
  • Publisher: Morgan Kaufmann (July 2006)
  • Language: English
  • ISBN-10: 0123695260
  • ISBN-13: 978-0123695260
Download [7.5 MiB]

You may also like...

Leave a Reply